SA555 (正在供货)精密定时器

描述

These devices ae pecision timing cicuits capable of poducing accuate time delays o oscillation. In the time-delay o mono-stable mode of opeation, the timed inteval is contolled by a single extenal esisto and capacito netwok. In the a-stable mode of opeation, the fequency and duty cycle can be contolled independently with two extenal esistos and a single extenal capacito.

The theshold and tigge levels nomally ae two-thids and one-thid, espectively, of VCC. These levels can be alteed by use of the contol-voltage teminal. When the tigge input falls below the tigge level, the flip-flop is set, and the output goes high. If the tigge input is above the tigge level and the theshold input is above the theshold level, the flip-flop is eset and the output is low. The eset (RESET) input can oveide all othe inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is eset, and the output goes low. When the output is low, a low-impedance path is povided between dischage (DISCH) and gound.

The output cicuit is capable of sinking o soucing cuent up to 200 mA. Opeation is specified fo supplies of 5V to 15V. With a 5-V supply, output levels ae compatible with TTL inputs.

特性

• Timing Fom Micoseconds to Hous
• Astable o Monostable Opeation
• Adjustable Duty Cycle
• TTL-Compatible Output Can Sink o SouceUp to 200 mA
• On Poducts Compliant to MIL-PRF-38535,All Paametes Ae Tested Unless Othewise Noted. On All Othe Poducts, Poduction Pocessing Does Not Necessaily IncludeTesting of All Paametes.